1. Field of the Invention
The present invention generally relates to off chip driver (OCD) circuits and, more particularly, to programmable variable impedance OCD circuits.
2. Description of the Related Art
In electrical systems, output drivers are used to drive input/output (I/O) devices or similar loads. In order to have efficient power transfer it is important that the impedance of the driver closely match the impedance of the load; the load comprising the impedance of the driven device as well as the impedance of the transmission line. Each output driver is set up with a certain voltage/impedance that matches the strength of the transmission line and I/O device being driven by that specific driver. Thus, I/O devices with a low drive strength would need an output driver with a high impedance, and high strength I/O devices require a low impedance driver. Since each output driver typically has only one impedance rating, an output driver driving a load other than the one it is designed for would result in too much or too little of the strength needed.
High performance output driver circuits require careful control of both current switching and output impedance characteristics. The former requirement, commonly referred to as dI/dt control, requires switching the driver on over a specified period of time, or switching multiple stages of the driver on in sequence. Such output current control techniques are necessary to minimize the on-chip inductive noise which occurs due to the large current requirements of the output driver circuits during switching. The driver impedance requirements result in xe2x80x9cprogrammable impedancexe2x80x9d drivers whose output resistance is varied using complicated digital controls. This impedance matching is necessary to avoid signal degradations due to bus reflections at high frequencies, where the output data bus acts as a transmission line.
As product cycle times decrease, the current control and programmable impedance design points for an output driver must be carefully considered to avoid limiting the performance of the driver. Variable impedance OCDs have become necessary as I/O bus architectures evolve from 66 MHZ single data rate (SDR) to 133 MHZ and higher double data rate (DDR) systems.
Simple prior art programmable impedance OCDs simply involved placing several fixed impedance off-chip drivers in parallel where each driver is commonly referred to in the art as a xe2x80x9cfingerxe2x80x9d. By enabling or disabling a selected number of fingers, usually with a control word, the combined impedance of the OCD varies. Several inefficiencies exist with this approach, such as the need for multiple Level Translators (LT) for data signals and control. For one thing, driver impedance needs to change incrementally from a control word and span over a wide impedance range. Further, impedance linearity over Vdq is difficult to preserve depending on the number of fingers selected. An ideal output driver having Vdq linearity would have the impedance characteristics of a resistor. That is, the current it supplies or sinks would be directly proportional to the voltage across the DQ output pin. In such an ideal driver, Vdq=Rdq*Idq. However, practical prior art output drivers are constructed from transistors, which have a linear and saturated range of operation. When the output transistor is biased in the linear region, the DQ current and voltage characteristics are substantially linear. However, at the edges of this linear range the transistor begins to saturate and current does not change proportionally with voltage, and output impedance rises orders of magnitude. It is therefore desirable for an OCD to have a predictably small percentage change in impedance over its range of Vdq, hence a high degree of linearity. It is also desirable to have this percentage change in impedance constant, independent of the numbers of fingers selected. In other words, if a 2% change in impedance occurs with a 7-ohm setting, a 2% change is preferred for a 17-ohm setting.
The present invention is directed to a multiple finger off chip driver (OCD) having a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the OCD to be varied to match the impedance of a driven load. A VSS-VDD level DATAIN input signal is supplied to both a PFET level translator (shifter) and an NFET level translator. The PFET level translator translates the DATAIN signal to a VDDQ level and the NFET level translator translates the DATAIN signal to a VSSQ level. The level translators can comprise either a single stage or dual stages. In the single stage DATAIN is stored in a first latch formed by PFET pull-up devices and NFET pull-down devices where the NFETs are sized to over power the PFETs. Hence, a DATAIN signal at a 1-volt high level is translated to a 3-volt VDDQ level because the drains of the PFETs are at 3 volt VDDQ. A TRIP input signal performs an enable function which must be at a logical low-level for the latch to accept DATAIN. The dual stage translator works much the same way as the single level translator described above to translate the VDD=1-volt DATAIN level to 3-volt VDDQ level. In addition, a VSS ground level is then translated to VSSQ ground level though a second latch such that the ouptu signal is referenced between VSSQ and VDDQ levels.
A plurality of PFET and NFET finger selection devices may be used to select various combinations of output FETS and ballast resistor finger combinations to drive the VDDQ-VSSQ output signal at a desired impedance level. The ballast resistors are scaled in ohmic value to the size of the output finger it is connected to. In this configuration, a constant ratio of FET impedance (as a function of FET width) to ballast resistance is maintained in each drive stage (finger). By selecting various combinations of fingers various driver impedances can be selected.